Fix/write vhdl shift pos operand types - #233
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tgingold merged 2 commits intoJun 22, 2026
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Three bugs in shift and $pos operand wrapping, all with the same root cause:
the handlers called dump_sigspec() directly on operands that require
dump_sigspec_unsigned/signed to produce legal VHDL-93.
t_shift_const: $shl/$shr/$sshl/$sshr with constant shift amount
to_integer(unsigned("000...001")) -- string literal is not a valid
type conversion operand. Refs ghdl#230.
t_shift_1bit: $shl/$shr with 1-bit signal shift amount
to_integer(unsigned(sig)) where sig is std_logic -- unsigned()
requires std_logic_vector. Refs ghdl#231.
t_pos_1bit: $pos extending a 1-bit signal (A_WIDTH=1, Y_WIDTH>1)
resize(unsigned(data), N) where data is std_logic -- same type
mismatch. Refs ghdl#232.
Co-authored-by: Claude Sonnet 4.6 <noreply@anthropic.com>
ghdl#232) Three related bugs in operand wrapping: the shift handlers and $pos called dump_sigspec() directly on operands that require dump_sigspec_unsigned/signed to handle 1-bit signals and constants. $shl/$shr/$sshl/$sshr, $shift, $shiftx (B operand): to_integer(unsigned("000...1")) -- string literal not a valid type conversion operand in VHDL-93. Refs ghdl#230. to_integer(unsigned(sig)) where sig is std_logic. Refs ghdl#231. Fix: use dump_sigspec_unsigned/signed for B throughout. $shl/$shr/$sshl/$sshr (A operand): unsigned(flag) where flag is std_logic. Fix: use dump_sigspec_unsigned/signed for A. $pos (A operand, a_width != y_width): resize(unsigned(data), N) where data is std_logic. Also fixes y_width==1 type mismatch via arith_open/close. Refs ghdl#232. Also extends t_shift_1bit.v to cover 1-bit A (shift of a std_logic value), and updates testsuite.sh comment to reflect the broader scope. Co-authored-by: Claude Sonnet 4.6 <noreply@anthropic.com>
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Closes #230
Closes #231
Closes #232
write_vhdl: fix shift and $pos operand type errors